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? 2016 microchip technology inc. ds20005612a-page 1 dsc400 features ? low rms phase jitter: <1 ps (typ.) ? high stability: 25 ppm, 50 ppm ? wide temperature range: - industrial ?40c to +85c - ext. commercial ?20c to +70c ? high supply noise rejection: ?50 dbc ? four format-configurable outputs: - lvpecl, lvds, hcsl, lvcmos ? available pin-selectable frequency table - 1 pin per bank for 2 frequency sets ? wide frequency range: - 2.3 mhz ? 460 mhz ? 20-pin qfn footprint (5.0 mm x 3.2 mm) ? excellent shock and vibration immunity ? high reliability - 20x better mtf than quartz-based devices ? wide supply range of 2.25v to 3.6v ? lead free and rohs-compliant ? aec-q100 automotive qualified applications ? communications and networks ? ethernet - 1g, 10gbase-t/kr/lr/sr, and fcoe ? storage area networks - sata, sas, fibre channel ? passive optical networks - epon, 10g-epon, gpon, 10g-pon ? hd/sd/sdi video and surveillance ? automotive ? media and video ? embedded and industrial general description the dsc400 is a four out put crystal-less? clock generator. it utilizes proven puresilicon? mems technology to provide excellent jitter and stability while incorporating additional device functionality. the nominal frequencies of the outputs can be identical or independently derived from common plls. each output may be configured independently to support a single-ended lvcmos interface or a differential interface. differential options include lvpecl, lvds, or hcsl. the dsc400 provides two independent select lines for choosing between two sets of pre-configured frequencies per bank. it also has two oe pins to allow for enabling and disabling outputs. the dsc400 is packaged in a 20-pin qfn (5 mm x 3.2 mm) and is available in extended commercial and industrial temperature grades. block diagram clk0+ bank 2 output control and dividers control circuitry mems pll oe1 oe2 fsb1 fsb2 bank 1 clk0- clk3+ clk3- clk1+ clk1- clk2+ clk2- pll configurable four output, low jitt er crystal-less? clock generator
dsc400 ds20005612a-page 2 ? 2016 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? supply voltage ................................................................................................................. ......................... ?0.3v to +4.0v input voltage .................................................................................................................. .....................?0.3v to v dd +0.3v esd protection (hbm) ........................................ ................................................................... ....................................4 kv esd protection (mm) ......... .............. .............. .............. .............. ........... ........... ........... .......... ....................................400v esd protection (cdm) ........................................ ................................................................... .................................1.5 kv ? notice: stresses above those listed under ?absolute maximu m ratings? may cause permanent damage to the device. this is a stress rating only and functiona l operation of the device at those or an y other conditions above those indicated in the operational sections of this s pecification is not intended. exposure to maximum rating conditions for extended periods may affect device reliability. electrical characteristics specifications: v dd = 3.3v; t a = +25c unless otherwise specified. parameters sym. min. typ. max. units conditions supply voltage ( note 1 )v dd 2.25 ? 3.6 v ? core supply current ( note 2 )i ddcore ? 40 44 ma oe(1:2) = 0. all outputs disabled. frequency stability ? f ? ? 25 ppm all temperature and v dd ranges. ??50 aging - first year ? f y1 ? ? 5 ppm one year at +25c aging - after first year ? f y2 + ? ? <1 ppm/yr year two and beyond at +25c start-up time ( note 3 )t su ? ? 5 ms t = +25c input logic levels v ih 0.75 x v dd ? ? v input logic high v il ? ? 0.25 x v dd input logic low output disable time ( note 4 )t da ? ? 5 ns oe(1:2) transition from 1 to 0 output enable time ( note 4 )t en ? ? 20 ns oe(1:2) transition from 0 to 1 pull-up resistor r pu ?40?k ? all input pins have an internal pull-up note 1: v dd pins should be filter ed with a 0.1 f capacitor connected between v dd and v ss . 2: the addition of i ddcore and i ddio provides the total current consumption of the device. 3: t su is time to 100 ppm stable output frequency after v dd is applied and outputs are enabled. 4: see the output waveform section for more information.
? 2016 microchip technology inc. ds20005612a-page 3 dsc400 temperature specifications ( note 1 ) parameters sym. min. typ. max. units conditions temperature ranges operating temperature range (t) t a ?20 ? +70 c ordering option e t a ?40 ? +85 c ordering option i junction temperature t j ? ? +150 c ? storage temperature range t s ?40 ? +150 c ? soldering temperature ? ? ? +260 c 40 sec. max. note 1: the maximum allowable power dissipation is a functi on of ambient temperature, the maximum allowable junction temperature, and the thermal resi stance from junction to air (i.e., t a , t j , ? ja ). exceeding the maximum allowable power dissipation will cause the dev ice operating junction te mperature to exceed the maximum +125c rating. sustained junction temperat ures above +125c can impa ct the device reliability.
dsc400 ds20005612a-page 4 ? 2016 microchip technology inc. 2.0 pin descriptions figure 2-1: pin configuration, 20-pin qfn (5.0 mm x 3.2 mm) the descriptions of the pins are listed in table 2-1 . table 2-1: pin function table pin number pin name pin type description 1 oe1 i output enable for bank1 (clk0 and clk3); active-high. see table 3-1 . 2 nc n/a leave unconnected or connect to ground. 3v ss pwr ground. 4v ss pwr ground. 5 clk0? o complement output of differential pair 0 (off when in lvcmos format). 6 clk0+ o true output of differential pair 0 or lvcmos output 0. 7 clk1? o complement output of differential pair 1 (off when in lvcmos format). 8 clk1+ o true output of differential pair 1 or lvcmos output 1. 9v dd2 pwr power supply for bank2 (clk1 and clk2). 10 fsb2 i input for selecting pre-configured frequencies on bank2 (clk1 and clk2). 11 oe2 i output enable for bank2 (c lk1 and clk2); active-high. see table 3-1 . 12 nc n/a leave unconnected or connect to ground. 13 v ss pwr ground. 14 v ss pwr ground. 15 clk2? o complement output of differential pair 2 (off when in lvcmos format). 16 clk2+ o true output of differential pair 2 or lvcmos output 2. 17 clk3? o complement output of differential pair 3 (off when in lvcmos format). 18 clk3+ o true output of differential pair 3 or lvcmos output 3. 19 v dd1 pwr power supply for bank1 (clk0 and clk3). 20 fsb1 i input for selecting pre-configured frequencies on bank1 (clk0 and clk3). oe2 11 nc vss vss 13 12 14 vss 4 vss nc oe1 2 3 1 clk0 - 5 clk0+ clk1 - clk1+ vdd2 fsb2 7 68910 clk2 - 15 clk2+ clk3 - clk3+ vdd1 fsb1 17 16 18 19 20
? 2016 microchip technology inc. ds20005612a-page 5 dsc400 3.0 operational description the dsc400 is a crystal-less? clock generator. unlike older clock generators in the industry, it does not require an external crystal to operate; it relies on the integrated mems resonator th at interfaces with internal plls. this technology enhances performance and reliability by allowing tighter frequency stability over a far wider temperature range . in addition, the higher resistance to shock and vibration decreases the aging rate to allow for much improved product life in the system. 3.1 inputs there are four input signals in the device. each has an internal (40 k ? ) pull-up to default the selection to a high (1). inputs can be controlled through hardware strapping method with a resistor to ground to assert the input low (0). inputs may also be controlled by other components? gpios in case more than one frequency set is desired, fsb1 and fsb2 are used to independently select one of two sets per bank. fsb1 selects the pre-configured set on bank1 (clk0 and clk3) and fsb2 selects the pre-configured set on bank2 (clk1 and clk2), as shown in table 1-1 in the product identification system section. if there is a requirement to disable outputs, the inputs oe1 and oe2 are used in conjunction to disable the banks of outputs. outputs are disabled in tri-state (hi-z) mode. see table 3-1 for more information. 3.2 outputs the four outputs are grouped into two banks. each bank is supplied by an independent v dd to allow for optimized noise isolation between the two banks. each bank provides two synchronous outputs generated by a common pll: ? bank1 is composed of outputs clk0 and clk3. ? bank2 is composed of outputs clk1 and clk2. each output may be pre-configured independently to be one of the following formats: lvcmos, lvds, lvpecl or hcsl. in case th e output is configured to be single-ended lvcmos, the frequency is generated on the true output (clkx+) and the complement output (clkx?) is shut off in a low state. frequencies can be chosen from 2.3 mhz to 460 mhz for differential outputs and from 2.3 mhz to 170 mhz on lvcmos outputs. 3.3 power v dd1 and v dd2 supply the power to banks 1 and 2 respectively. each v dd may each have a different supply voltage from the other as long as it is within the 2.25v to 3.6v range. each v dd pin should have a 0.1 f capacitor to filter high-frequency noise. v ss is common to the entire device. table 3-1: output enable selection table oe1 oe2 bank 1 (clk0 & clk3) bank 2 (clk1 & clk2) 0 0 hi-z hi-z 0 1 hi-z running 1 0 running hi-z 1 1 running running
dsc400 ds20005612a-page 6 ? 2016 microchip technology inc. 4.0 termination schemes 4.1 lvpecl figure 4-1: typical lvpecl termination scheme. note 1: lvpecl applicable to extended commercial temperature only. 2: see the output waveform section for more information. 3: the addition of i ddcore and i ddio provides the total current consumption of the device. 4: period jitter includes cro sstalk from adjacent output. v dd 100 130 82 130 82 table 4-1: lvpecl outputs ( note 1 ) parameter symbol min. typ. max. units condition output logic levels v oh v dd ? 1.08 ? ? v output logic high, r l = 50 ? to v dd ?2v v ol ??v dd ? 1.55 output logic low, r l = 50 ? to v dd ?2v peak-to-peak output swing ? ? 800 ? mv single-ended output transition time ( note 2 ) t r ? 250 ? ps rise time. 20% to 80%; r l = 50 ? to v dd ?2v t f ? 250 ? fall time. 20% to 80%; r l = 50 ? to v dd ?2v frequency f 0 2.3 ? 460 mhz single frequency output duty cycle sym 48 ? 52 % differential io supply current ( note 3 ) i ddio ? 35 38 ma per output at 125 mhz period jitter ( note 4 ) j per ?2.5?ps rms clk(0:3) = 156.25 mhz integrated phase noise j ph ?0.25?ps rms 200 khz to 20 mhz @ 156.25 mhz ? 0.38 ? 100 khz to 20 mhz @ 156.25 mhz ? 1.7 2 12 khz to 20 mhz @ 156.25 mhz
? 2016 microchip technology inc. ds20005612a-page 7 dsc400 4.2 lvds figure 4-2: typical lvds termination scheme. if the 100 ? clamping resistor does not exist inside the receivin g device, it should be added externally on the pcb and placed as close as possible to the receiver. note 1: see the output waveform section for more information. 2: the addition of i ddcore and i ddio provides the total current consumption of the device. table 4-2: lvds outputs parameter symbol min. typ. max. units condition output offset voltage v os 1.125 ? 1.4 v r = 100 ? differential delta offset voltage ? v os ??50mv? peak-to-peak output swing v pp ? 350 ? mv single-ended output transition time ( note 1 ) t r ? 200 ? ps rise time, 20% to 80%, r l = 50 ? , c l = 2 pf t f ? 200 ? fall time, 20% to 80%, r l = 50 ? , c l = 2 pf frequency f 0 2.3 ? 460 mhz single frequency output duty cycle sym 48 ? 52 % differential io supply current ( note 2 ) i ddio ? 9 12 ma per output at 125 mhz. period jitter j per ?2.5?ps rms ? integrated phase noise j ph ?0.28?ps rms 200 khz to 20 mhz @ 156.25 mhz ? 0.4 ? 100 khz to 20 mhz @ 156.25 mhz ? 1.7 2.0 12 khz to 20 mhz @156.25 mhz 100 100 load (receiver ic)
dsc400 ds20005612a-page 8 ? 2016 microchip technology inc. 4.3 hcsl figure 4-3: typical hcsl termination scheme. r s is a series resistor implemented to match the trace impedance. depending on the board layout, the value may range from 0 ? to 30 ? . note 1: see the output waveform section for more information. 2: the addition of i ddcore and i ddio provides the total current consumption of the device. table 4-3: hcsl outputs parameter symbol min. typ. max. units condition output logic levels v oh 0.725 ? ? v output logic high, r l = 50 ? v ol ? ? 0.1 output logic low, r l = 50 ? peak-to-peak output swing ? ? 750 ? mv single-ended output transition time ( note 1 ) t r 200 ? 400 ps rise time, 20% to 80%, r l = 50 ? , c l = 2 pf t f 200 ? 400 fall time, 20% to 80%, r l = 50 ? , c l = 2 pf frequency f 0 2.3 ? 460 mhz single frequency output duty cycle sym 48 ? 52 % differential io supply current ( note 2 ) i ddio ? 20 22 ma per output at 125 mhz. period jitter j per ?2.5?ps rms ? integrated phase noise j ph ?0.25?ps rms 200 khz to 20 mhz @ 156.25 mhz ? 0.37 ? 100 khz to 20 mhz @ 156.25 mhz ? 1.7 2.0 12 khz to 20 mhz @156.25 mhz 100 50 50 r s r s
? 2016 microchip technology inc. ds20005612a-page 9 dsc400 4.4 lvcmos figure 4-4: typical lvcmos termination scheme. r s is a series resistor implemented to match the trace impedance to that of th e clock output. depending on the board layout, the value may range from 0 ? to 27 ? . note 1: see the output waveform section for more information. 2: the addition of i ddcore and i ddio provides the total current consumption of the device. table 4-4: lvcmos outputs parameter symbol min. typ. max. units condition output logic levels v oh 0.9 x v dd ? ? v output logic high, i = 6 ma v ol ? ? 0.1 x v dd output logic low, i = 6 ma output transition time ( note 1 ) t r ? 1.1 2.0 ns rise time, 20% to 80%, c l = 15 pf t f ? 1.3 2.0 fall time, 20% to 80%, c l = 15 pf frequency f 0 2.3 ? 170 mhz all temperature ranges, except automotive ? ? 100 automotive temperature range output duty cycle sym 44 ? 55 % ? io supply current ( note 2 ) i ddio ? 11 14 ma per output at 125 mhz, c l = 15 pf period jitter j per ?3?ps rms clk(0:3) = 125 mhz integrated phase noise j ph ?0.3?ps rms 200 khz to 20 mhz @ 125 mhz ? 0.38 ? 100 khz to 20 mhz @ 125 mhz ? 1.7 2.0 12 khz to 20 mhz @125 mhz 50 r s
dsc400 ds20005612a-page 10 ? 2016 microchip technology inc. 5.0 output waveform figure 5-1: differential output (l vds, lvpecl, hcsl). figure 5-2: lvcmos output. oe t r t f 1/f 0 t da t en clk clk v il v ih 50% 20% 80% oe t r t f 1/f 0 t da t en clk v il v ih v ol v oh
? 2016 microchip technology inc. ds20005612a-page 11 dsc400 6.0 connection diagram the connection diagram below includes recommended capacitors to be placed on each v dd for noise filtering. figure 6-1: dsc400 connection diagram. frequency select 1 oe2 nc vss vss vss vss nc oe1 clk0 ? clk0+ clk1 ? clk1+ vdd2 fsb2 clk2 ? clk2+ clk3 ? clk3+ vdd1 fsb1 frequency select 2 v dd output enable 1 output enable 2 v dd clock 3 output clock 2 output clock 0 output clock 1 output 0.1f 0.1f
dsc400 ds20005612a-page 12 ? 2016 microchip technology inc. 7.0 solder reflow profile time 150c 200c 260c temperature 60-180 seconds 60-150 seconds cooldown reflow preheat 20-40 seconds 8 minutes max. 25c 6 c / sec max . 3 c / sec max . 3 c/ sec max. 217c msl 1 @ 260 c refer to jstd-020c ramp-up rate (200c to peak temp) 3c/sec. max. preheat time 150c to 200c 60-180 sec. time maintained above 217c 60-150 sec. peak temperature 255c to 260c time within 5c of actual peak 20-40 sec. ramp-down rate 6c/sec. max. time 25c to peak temperature 8 minutes max.
? 2016 microchip technology inc. ds20005612a-page 13 dsc400 8.0 package marking information 20-lead qfn 5.0 mm x 3.2 mm package outline and recommended land pattern note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging.
dsc400 ds20005612a-page 14 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005612a-page 15 dsc400 appendix a: revision history revision a (september 2016) ? converted micrel data sheet dsc400 to micro- chip ds20005612a. ? minor text changes throughout.
dsc400 ds20005612a-page 16 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005612a-page 17 dsc400 product identification system to order or obtain information, e.g., on pricing or delivery, contact your local microchip representative or sales office . 1.0 factory configuration co de assignment of qxxxx the dsc400 is meant for customers to define their own fre quency requirements at the f our available outputs. the qxxxx number identifies these specific customer r equirements and is assigned by the factory. table 1-1: example of how fsb1 & fsb2 are applied & the qxxxx assignment bank1 outputs fsb1 qxxxx number 1 (default) 0 q0001 clk0 125 mhz 150 mhz clk3 50 mhz 25 mhz bank2 outputs fsb2 1 (default) 0 clk1 156.25 mhz 100 mhz clk2 156.25 mhz 100 mhz examples: a) dsc400-2143qxxxxke1t: configurable four output, low jitter crystal-less clock generator; lvpecl clk3; lvcmos clk2; hcsl clk1; lvds clk0; frequency code; 20-pin qfn; ?20c to +70c temp. range; 50 ppm stabil- ity; tape & reel b) dsc400-4132qxxxxki2t: configurable four output, low jitter crystal-less clock generator; hcsl clk3; lvcmos clk2; lvds clk1; lvpecl clk0; frequency code; 20- pin qfn; ?40c to +85c temp. range; 25 ppm stability; tape & reel c) dsc400-0202qxxxxke2t: configurable four output, low jitter crystal-less clock generator; off clk3; lvpecl clk2; off clk1; lvpecl clk0; frequency code; 20-pin qfn; ?20c to +70c temp. range; 25 ppm stability; ta p e & r e e l d) dsc400-1111qxxxxki1t: configurable four output, low jitter crystal-less clock generator; lvcmos clk3 through clk0; frequency code; 20-pin qfn; ?40c to +85c temp. range; 50 ppm stability; tape & reel part no. x x package stability device device: dsc400: configurable four output, low jitter crystal-less clock generator clk3 output format: 0=off 1=lvcmos 2 = lvpecl 3=lvds 4 = hcsl clk2 output format: 1=lvcmos 2 = lvpecl 3=lvds 4=hcsl clk1 output format: 0=off 1=lvcmos 2 = lvpecl 3=lvds 4 = hcsl clk0 output format: 1=lvcmos 2 = lvpecl 3=lvds 4 = hcsl frequency code: qxxxx = this code is assigned by the factory. see the table in this section for more information. package: k=20-pin qfn temperature range: e = ?20c to +70c i = ?40c to +85c stability: 1=50 ppm 2=25 ppm packing: t=tape & reel x clk3 x temp. qxxxx freq. output format x clk2 output format x clk1 output format x clk0 output format code range x packing
dsc400 ds20005612a-page 18 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005612a-page 19 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microc hip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered tradem arks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0985-4 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microper ipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem by dnv == iso/ts 16949 ==
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